Learn to build OVM & UVM Testbenches from scratch

Learn and Start building Verification Testbenches in SystemVerilog based Verification Methodologies – OVM and UVM

Description

The Verification industry is adopting SystemVerilog based UVM Methodology at a rapid pace for most of the current ASIC/SOC Designs and is considered as a key skill for any job in the front end VLSI design/verification jobs.

This course teaches

• Basic concepts of two (similar) methodologies – OVM and UVM –
• Coding and building actual testbenches based on UVM from grounds up.
• Plenty of examples along with assignments (all examples uses UVM)
• Quizzes and Discussion forums
• Hands on assignment to build a complete UVM Verification environent for a most popular SOC Bus protocol – APB Bus

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